The present invention relates to a dynamic semiconductor integrated circuit, and more particularly, to achievement of speedup and malfunction protection during low-voltage operation.
Dynamic circuits are used for circuits requiring high-speed operation such as memory circuits. Use of static circuits for such circuits will increase the gate capacitance preventing high-speed operation.
A semiconductor integrated circuit using a dynamic circuit is disclosed in Japanese Laid-Open Patent Publication No. 2003-318727. The disclosed circuit is provided with a hold circuit having an inverter and a p-channel metal oxide semiconductor (PMOS) transistor for protection against a malfunction. The input terminal of the inverter is connected to an output node, the gate of the PMOS transistor is connected to the output of the inverter, and the drain of the PMOS transistor is connected to the output node, so that the PMOS transistor can supply charge to the output node.
Assume that such a semiconductor integrated circuit is used for a circuit for decoding an address, for example. When the capability of the PMOS transistor of the hold circuit is increased, occurrence of a malfunction can be prevented if the address misses in the decoding circuit (that is, if the potential of the precharged output node is kept high). However, if the address hits in the circuit (that is, if the potential of the precharged output node must be lowered), the following problem occurs when the power supply voltage is low, in particular. That is, the charge at the output node cannot be drawn sufficiently with an n-channel metal oxide semiconductor (NMOS) transistor, and thus speedup of the operation fails.
When the capability of the PMOS transistor of the hold circuit is reduced, the charge at the output node can be drawn even when the power supply voltage is low if the address hits in the circuit. However, if the address misses in the circuit, a glitch may grow and cause the possibility of a malfunction.